Description:
- Responsible for designing and developing various innovative projects, including the Memory Controller and DRAM Test Engine projects etc.
- Understand the system requirements of the digital functions and develop specifications.
- Microarchitecture of RTL code aimed for high performance, low area and low power design. Implement the function in Verilog or System Verilog according to specification. Perform IP level simulation and regression test with the design modules.
- Perform IP level synthesis and timing closure. Optimize the design for high performance, low area and low power.
- Support the DV team by providing design insights for test plan design and test design, debugging and fixing failing test cases and writing self-checking tests as required.
- Support all design integration activities like LINT, CDC, synthesis and logical equivalence etc.
Requirements:
- MS in Electrical Engineering, Computer Engineering or related field and one (1) year experience
- Research and development of digital IPs
- RTL coding in Verilog
- Digital IP microarchitecture design
- Simulation tools and methodology such as UVM
- Code management tools such as SVN
