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Computer System Architect

Job Code: SA001


Description:

  • Work closely with IP architects to establish and document platform and system requirements for the IP's to function optimally
  • Work across multiple teams and organizations that are involved with the integration and enabling for these complex IP blocks.

Requirements:

  • MS EE/CS+5 year of experience or PhD EE/CS
  • Deep expertise in system architecture fundamentals.
  • Computer and SoC architectures
  • Hardware/Firmware/Software partitioning
  • Strong physical concepts, including high-speed PHY specs, packaging, thermal solutions, and power supplies
  • Strong communication, persuasion and negotiation skills in addition to being comfortable with working through ambiguities

Plus Skills:

  • Experience designing high volume products from beginning to end as well as experience creating and influencing system specification documents

Staff PCIe Design Engineer

Job Code: SD001


Job Duties:

Responsible for all aspects of SoC design and chip bring up. Work with members of the SoC Design and Verification, System Verification, Firmware, Emulation, and Physical Design teams. Deliver working PCIe hardware solutions within the SoC Develop micro-architecture and design specifications. Implement and verify complex logic designs. Hands-on verification and validation on emulation platforms running with the SW drivers. 


Requirements

  • MS EE/CS+5 year of experience or PhD EE/CS 
  • Experience of PCIe root complex and end points
  • Verilog RTL logic design experience of multi-million gate ASICs
  • Experience writing specifications and converting them to design
  • Experience with bring up and lab debug of FPGAs prototyping and silicon
  • Experience with commercial PCIe IPs such as Synopsys. Good communication  with IP vendors.


Plus Skills:

  • Experience in NVMe
  • Knowledge of various DMA architectures
  • Knowledge of next-gen interconnect fabric protocol (OpenCAPI, CXL, CCIX, GenZ) 

Senior Design Engineer

Job Code: SD002


Job Duties:

  • Design DDR SDRAM memory controllers and high performance ASIC for embedded processors using the Final Level Cache Architecture.
  • Understand the system requirements of the digital functions and develop specifications. 
  • Define micro-architecture and conduct logic design applying knowledge in Computer Architecture, including: out-of-order execution, super scalar and pipeline, data hazard, cache/memory subsystems, CDC, and DDR SDRAM controller. 
  • Conduct RTL logic design with Verilog and/or SystemVerilog using tools, including: Synopsys VCS, Verdi, Spyglass, and Design Compiler, Cadence Incisive NC-verilog, NC-sim, and Xcelium. 
  • Perform logic synthesis, IP level verification, timing analysis, and resolve timing violations using Synopsys PrimeTime. 
  • Report logic design issues, optimize design, perform CDC and resolve errors in cache and memory subsystem. 
  • Support the Design Verification team by providing design insights for test planning, debugging, and fixing failing test cases. 
  • Support all design integration activities like LINT, CDC, and synthesis. 


Requirements:

  • Master’s degree in Electrical Engineering and two years of experience in research and development of embedded processors and DDR SDRAM controller
  • Logic design, logic synthesis, and verification and timing analysis of high performance ASIC
  • Develop methods to improve design, and resolve errors involving cache/memory subsystem and CDC
  • Logic design of various components in memory controller using RTL (mainly Verilog / System Verilog)
  • Perform logic synthesis using Synopsys Design Compiler
  • Experience in the micro-architecture definition of memory controllers, design verification and debugging
  • Perform timing analysis and identify fixes on any timing violations using Synopsys PrimeTime.


HPC Infrastructure Engineer/Contractor

Job Code: IT001


Job Duties:

  • Design, deploy and maintain scalable high-performance-computing platforms for engineering works
  • Develop and maintain on-premise/in-cloud/hybrid computing platform.
  • General on-site support for IT: infrastructure, networking and equipment deployment and maintenance. 

Requirements:

  • Experience in HPC infrastructure deployment and operations.
  • Experience with Linux operating system flavors (CentOS/RHEL).
  • Experience with containers (Singularity, Docker, Kubernetes) and job schedulers (Slurm, LSF)

Plus skills:

  • Experience with EDA tool (Simulation, Synthesize, Place and Route) flow and workload requirements.

Technical Program Manager

Job Code: PM001


Description:

  • Drive program schedules and resolve technical issues that enable on time program delivery. 
  • Collaborate with multi-functional teams to foresee and resolve technical issues blocking program delivery starting with architectural definition to product delivery and beyond.

Requirements:

  • 7+ years experience in SOC / VLSI Chip Design, DRAM, Product Engineering.
  • 5+ years of Technical program management / vendor management experience.
  • Extraordinary leadership skills and ability to inspire team members with an innate ability to see the bigger picture.
  • Passion to own/drive project development using well-defined metrics.
  • Experience working in a high-energy multi-disciplined engineering environment, strong at multi-tasking, and real-time crisis management.
  • Thrive in dynamic schedule driven development environment.
  • Ability to understand and extract action plans from complex technical discussions and translate into succinct messaging for multi-functional and executive status reporting.

Plus Skills:

  • Experience with ARM architecture and leading silicon projects from concept to production.

Technical Writer

Job Code: TR001


Description:

  • Produce high-quality, custom documentation that contributes to the success of our program.
  • Responsible for producing the technical manuals as well as documenting specification and procedures in conjunction with the engineering team.

Requirements:

  • 4 year college degree or commensurate experience.
  • Background in technology, computer hardware and electronics.
  • Highly skilled at formatting text and graphics for technical documentations.
  • Excellent writing skills and great verbal/interpersonal communication skills.
  • Adept at accessing and utilizing engineering drawings and databases.
  • Must be able to multi-task well, gather information quickly, and complete manuals on time.

Plus Skills:

  • Experience with synthesize and align technical content and specifications from different vendor partners.

Senior Digital Design Engineer

Job Code: DE001


Job Duties: 

Understand the system requirements of the digital functions and develop specifications. Microarchitecture of RTL code aimed for high performance, low area and low power design. Implement the function in Verilog or System Verilog according to specification. Perform IP level simulation and regression test with the design modules. Perform IP level synthesis and timing closure. Optimize the design for high performance, low area and low power. Support the DV team by providing design insights for test plan design and test design, debugging and fixing failing test cases and writing self-checking tests as required. Support all design integration activities like LINT, CDC, synthesis and logical equivalence.


Requirements:  

MS in Electrical Engineering and two years’ experience in ASIC design, including the experience in RTL logic design with Verilog or System Verilog, experience in the ASIC design flow with front-end tools: Synopsys VCS, Verdi and Spyglass, micro-architecture, and ASIC design skills, experience with computer architecture especially out-of-order execution, super scaler and pipeline, data hazard, cache/memory subsystem, CDC, and DDR SDRAM controller.

Staff Verification Engineer

Job Code: DV001


Job Duties: 

Apply advanced verification methodologies to verify memory subsystem designs of the computer systems, including the AMBA5 CHI and AMBA4 AXI bus bridges, the final level caches, the DDRx/LPDDRx memory controllers, and the interfaces with DDR PHY. Interact with design and micro-architecture teams to review design specifications and understand the functional requirements of the design; execute verification tasks to ensure correctness of functionalities in the design; write functional test plans; build UVM-based constrained random test benches, including sequencers, generators, drivers, scoreboard, monitors, checkers, and integrate with CHI/AXI verification IPs; write test cases; build Perl/Python scripts to automate the regression tasks; run simulation using Synopsys VCS or Mentor Questa; debug and report failures in the design; collect functional coverage and code coverage; use coverage tools to analyze and tweak tests for coverage; apply assertion-based verification methodology to facilitate debug; support system integration; build performance test benches on Emulators for silicon bring-up.


Requirements: 

Master’s degree in Electrical Engineering and four years of experience in design verification, including review specifications, develop attributes, test and coverage plans, define methodology and test benches; work with design and micro-architecture teams to understand the functional and performance goals of the design; develop and execute block/top level/full chip tests and triage of failures; experiences in the following tools: Python scripting, Verilog/SystemVerilog/UVM; RTL simulation tools (Synopsys, VCS, Mentor Questa); domain knowledge of ONFI, AXI, ACE.

Logic Design and Verification Engineer

Job Code: DG001


Description: 

  • Logic design/synthesis/timing analysis or Logic Verification/Test Coverage 
  • Responsible for design or verification, and presentation documents 


Requirements: 

  • MS EE/CS or BS EE/CS+2 years of experience
  • Deep knowledge on Computer Architecture especially: out-of-order execution, data hazard, cache/memory subsystems, and simulation tools 
  • Digital system designers: must have experience in design specification, microarchitecture, RTL logic implementation in Verilog
  • Verification engineers: must have experience in advanced verification methodologies such as constrained random test benches, assertion, functional coverage, code coverage and UVM 
  • Team player and an optimist: able to work with teams in multiple office sites 

Plus Skills: 

  • Bus protocol knowledge: ARM AMBA AXI/ACE/CHI or Intel QPI. 
  • Deep knowledge of DDR4, LP4, WIO2, and Cache hierarchy design and optimization of advanced memory controller 
  • Fluent in System Verilog, SVA, C++ or assembly language 
  • Experience with FPGA/emulator (Palladium/Veloce)